dtmc
const int B_RP = 1000;
const int S_RP = 1;
const int B_IP = S_RP;
const int S_IP = B_RP;
const int Tb = 50;
const int TbB =20;
const int Ts = 50;
const int TsB = 48;
const int bCinc = 100;
const int bBinc = 1;
const int sCdec = 100;
const int sBdec = 1;
const int Kb = 1;
const int Ks = 8;
const Offset = 10000;
module Buyer
b:[0..6] init 0;
bid :[B_IP..B_RP] init B_IP;
tb:[0..Tb] init 0;
Bcon : bool init false;
Bstop : bool init false;
Bswitch :bool init false;
Bagreed:bool init false;
[] b=0 & !Bswitch & Bcon & B_RP-bid>Kb*bCinc -> 1 : (b'=1);
[] b=0 & !Bswitch & !Bcon & tb<TbB -> 1 : (b'=1);
[] b=0 & Bswitch -> 1 : (b'=1);
[] b=0 & !Bswitch & Bcon & B_RP-bid<=Kb*bCinc
-> 1 : (b'=1) & (Bcon'=false) & (Bswitch'=true);
[] b=0 & !Bswitch & !Bcon & tb=TbB
-> 1 : (b'=1) & (Bcon'=true) & (Bswitch'=true);
[BID] b=1 & Sstop ->1 : (b'=4);
[BID] b=1 & tb=0 & !Sstop -> 1 : (b'=6) & (tb'=tb+1);
[BID] b=1 & Bcon & tb>0 & tb<Tb-1 & B_RP-bid>bCinc & !Sstop ->
1 : (b'=6) & (bid'=bid+bCinc) & (tb'=tb+1);
[BID] b=1 & !Bcon & (tb>0 & tb<Tb-1) & (B_RP-bid)>bBinc & !Sstop ->
1 : (b'=6) & (bid'=bid+bBinc)& (tb'=tb+1);
[BID] b=1 & tb>0 & Bcon & !Sstop & (tb=Tb-1 | (tb<Tb-1 & B_RP-bid<=bCinc)) ->
1 : (b'=6) & (bid'=B_RP) & (tb'=tb+1) & (Bstop'=true);
[BID] b=1 & tb>0 & !Bcon & !Sstop & (tb=Tb-1 | (tb<Tb-1 & B_RP-bid<=bBinc)) ->
1 : (b'=6) & (bid'=B_RP) & (tb'=tb+1) & (Bstop'=true);
[] b=6 & !Bswitch & Bcon & B_RP-bid>Kb*bCinc -> 1 : (b'=2);
[] b=6 & !Bswitch & !Bcon & tb<TbB -> 1 : (b'=2);
[] b=6 & Bswitch -> 1 : (b'=2);
[] b=6 & !Bswitch & Bcon & B_RP-bid<=Kb*bCinc
-> 1 : (b'=2) & (Bcon'=false) & (Bswitch'=true);
[] b=6 & !Bswitch & !Bcon & tb=TbB
-> 1 : (b'=2) & (Bcon'=true) & (Bswitch'=true);
[] b=2 & s=2 -> 1 : (b'=3) & (Bagreed'=true);
[CBID] b=2 & !Bstop -> 1 : (b'=4);
[CBID] b=2 & Bstop -> 1 : (b'=5);
[PURCHASE] b=3 -> 1 : (b'=3);
[] b=4 & Bcon & tb<Tb-1 & bid+bCinc>=cbid -> 1 : (b'=3);
[] b=4 & Bcon & tb=Tb-1 & B_RP>=cbid -> 1 : (b'=3);
[] b=4 & Bcon & !Sstop & ((tb<Tb-1 & bid+bCinc<cbid) | (tb=Tb-1 & B_RP<cbid)) ->
max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=3)
+ 1-max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=0);
[] b=4 & Bcon & Sstop & ((tb<Tb-1 & bid+bCinc<cbid) | (tb=Tb-1 & B_RP<cbid)) ->
max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=3)
+ 1-max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=5);
[] b=4 & !Bcon & tb<Tb-1 & bid+bBinc>=cbid -> 1 : (b'=3);
[] b=4 & !Bcon & tb=Tb-1 & B_RP>=cbid -> 1 : (b'=3) ;
[] b=4 & !Bcon & !Sstop & tb<Tb-1 & bid+bBinc<cbid ->
max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=3)
+ 1-max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=0);
[] b=4 & !Bcon & (Sstop=true) & (tb<Tb-1) & ((bid+bBinc)<cbid)->
max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=3)
+ 1-max(0,1 + (S_RP+Offset)/(cbid-(B_RP+S_RP+Offset))) : (b'=5);
[STOP] b=5 -> 1 : (b'=5);
endmodule
module Seller
s:[0..7] init 0;
cbid :[S_RP..S_IP] init S_IP;
ts:[0..Ts] init 0;
Scon: bool init true;
Sstop: bool init false;
Sswitch :bool init false;
[BID] s=0 & !Bstop & !Sstop -> 1 : (s'=1);
[BID] s=0 & (Bstop | Sstop) -> 1 : (s'=5);
[] s=1 & Scon & cbid-sCdec<=bid -> 1 : (s'=2);
[] s=1 & Scon & !Bstop & cbid-sCdec>bid
-> max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=2)
+ 1-max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=6);
[] s=1 & Scon & Bstop & cbid-sCdec>bid
-> max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=2)
+ 1-max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=5);
[] s=1 & !Scon & ts<Ts-1 & cbid-sBdec<=bid -> 1 : (s'=2);
[] s=1 & !Scon & ts=Ts-1 & cbid-sBdec<=bid -> 1 : (s'=2);
[] s=1 & !Scon & !Bstop & cbid-sBdec>bid
-> max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=2)
+ 1-max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=6);
[] s=1 & !Scon & Bstop & cbid-sBdec>bid
-> max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=2)
+ 1-max(0,1-(S_RP+Offset)/(bid+Offset)) :(s'=5);
[PURCHASE] s=2 -> 1 : (s'=2);
[] s=6 & !Sswitch & Scon & cbid-S_RP>Ks*sCdec -> 1 : (s'=3);
[] s=6 & !Sswitch & !Scon & ts<TsB -> 1 : (s'=3);
[] s=6 & Sswitch -> 1 : (s'=3);
[] s=6 & !Sswitch & Scon & cbid-S_RP<=Ks*sCdec ->
1 : (s'=3) & (Scon'=false) & (Sswitch'=true);
[] s=6 & !Sswitch & !Scon & ts=TsB ->
1 : (s'=3) & (Scon'=true) & (Sswitch'=true);
[CBID] s=3 & Bstop ->1 : (s'=5);
[CBID] s=3 & ts=0 & !Bstop -> 1 : (s'=7) & (ts'=ts+1);
[CBID] s=3 & Scon & !Bstop & ts>0 & ts<Ts-1 & cbid-S_RP>sCdec ->
1 : (s'=7) & (cbid'=cbid-sCdec) & (ts'=ts+1);
[CBID] s=3 & !Scon & !Bstop & ts>0 & ts<Ts-1 & cbid-S_RP>sBdec ->
1 : (s'=7) & (cbid'=cbid-sBdec) & (ts'=ts+1);
[CBID] s=3 & ts>0 & Scon & !Bstop & (ts=Ts-1 | (ts<Ts-1 & cbid-S_RP<=sCdec)) ->
1 : (s'=7) & (cbid'=S_RP) & (ts'=ts+1) & (Sstop'=true);
[CBID] s=3 & ts>0 & !Scon & !Bstop & (ts=Ts-1 | (ts<Ts-1 & cbid-S_RP<=sBdec)) ->
1 : (s'=7) & (cbid'=S_RP) & (ts'=ts+1) & (Sstop'=true);
[] s=4 & b=1 -> 1 : (s'=0);
[] s=4 & b=3 -> 1 : (s'=2);
[STOP] s=5 -> 1 : (s'=5);
[] s=7 & !Sswitch & Scon & cbid-S_RP>Ks*sCdec -> 1 : (s'=4);
[] s=7 & !Sswitch & !Scon & ts<TsB -> 1 : (s'=4);
[] s=7 & Sswitch -> 1 : (s'=4);
[] s=7 & !Sswitch & Scon & cbid-S_RP<=Ks*sCdec ->
1 : (s'=4) & (Scon'=false) & (Sswitch'=true);
[] s=7 & !Sswitch & !Scon & ts=TsB ->
1 : (s'=4) & (Scon'=true) & (Sswitch'=true);
endmodule